// Copyright (C) 1953-2022 NUDT
// Verilog module name - measure_clock_timing 
// Version: V4.0.0.20221115
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         global time synchronization 
//         generate report pulse base on global time
///////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module measure_clock_timing
#(
    parameter clk_period = {8'd8,41'h0}//8ns
 )  
(
        i_clk,
        i_rst_n,
        
        ov_mea_clk
);
// clk & rst
input                  i_clk;
input                  i_rst_n;

output reg [95:0]      ov_mea_clk;            

always @(posedge i_clk or negedge i_rst_n) begin//local time rst 
    if(!i_rst_n)begin
        ov_mea_clk    <= 96'b0;
    end
    else begin
		if(ov_mea_clk[47:0] >= ({32'd1000000000,16'b0} - clk_period[48:25]))begin
		    ov_mea_clk[95:48] <= ov_mea_clk[95:48] + 1'b1;
		    ov_mea_clk[47:0]  <= ov_mea_clk[47:0] + clk_period[48:25] - {32'd1000000000,16'b0};
		end
		else begin
		    ov_mea_clk[95:48] <= ov_mea_clk[95:48];
		    ov_mea_clk[47:0]  <= ov_mea_clk[47:0] + clk_period[48:25];
		end
    end
end
endmodule